1. Field of the Invention
The present invention relates in general to a semiconductor memory device, and more particularly to a stacked-gate flash memory device.
2. Description of the Related Arts
In the era of portable systems, flash memory technology is driven to develop a high-density cell with low bit cost and low power consumption.
To realize low bit cost, it is indispensable to reduce the cell size and the number of process steps. For significant reduction in cell size, self-aligned shallow trench isolation (STI) is proposed. The use of STI results in minimized bit line pitch and small cell size.
A high-density flash memory is described in the article xe2x80x9cA 0.15 xcexcm NAND Flash Technology with 0.11 xcexcm2 Cell size for 1 Gbit Flash memory,xe2x80x9d Jung-Dal Choi et al., IEEE, 2000. To interconnect the NAND cell array, the poly-Si source is connected to every string as a common line and the tungsten bit line is damascened over the entire string. These double-layers interconnection leads to simple process and reduced steps.
Another high-density flash memory is described in the article xe2x80x9cNovel 0.44 xcexcm2 Ti-Salicide STI cell Technology for High Density NOR Flash Memories and High Performance Embedded Application,xe2x80x9d H. Watanabe et al., IEEE, 1998. The high-density flash memory has shallow trench isolation, Ti-silicided polysilicon gate and source/drain, and tungsten local inter-connect source line.
An object of the invention to provide a novel stacked-gate flash memory structure.
The memory device of the present invention is featured by comprising a source line between gate electrode stacks that has a surface level below a top surface of the stacks. Such xe2x80x9crecessedxe2x80x9d source line prevents short between source line and control gate when the control gate is exposed from source line opening due to misalignment.
In addition, the memory device of the present invention is featured by comprising shallow trench isolation structures that are recessed below the substrate surface. Such recessed isolation regions can provide low resistance and reduce flash cell size.
The memory device of the present invention comprises: a semiconductor substrate; a tunnel oxide layer on the substrate; an array of gate electrode stacks formed on the tunnel oxide layer, the gate electrode stacks including a floating gate electrode over the tunnel oxide layer, an inter-gate dielectric layer over the floating gate electrode, a control gate electrode over the inter-gate dielectric layer; alternating source/drain regions formed between the stacks; a first dielectric layer over the stacks, and the substrate, the first dielectric layer having a source line opening down to the source regions; a source line partially filling the source line opening and contacting the source regions through the source line openings, the source line being located between the stacks and having a surface level below a top surface of the stacks; a second dielectric layer over the source line and the first dielectric layer, the second dielectric layer having a plug opening down to the drain regions; a drain metal plug filling the plug opening in contact with the drain regions, the drain metal plug being located over the drain regions and between the stacks; and a metal bit line formed over the second dielectric layer contacting the drain metal plug. Furthermore, the memory device may further comprise shallow trench isolation (STI) structures have a surface level below the substrate surface, and preferably between the substrate surface and the junction depth of the source/drain regions.